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CDB61310 T1 Long Haul Line Interface Unit
Features
l Socketed
Description
The evaluation board includes a socketed CS61310 line interface device and all support components necessary for evaluation. The board is powered by an external +5 Volt supply. The board is configured for 100 twisted-pair T1 long haul operations. Binding posts and bantam jacks are provided for the line interface connections. Several BNC connectors provide clock and data I/O at the system interface. Reference timing may be derived from a quartz crystal or an external reference clock. Four LED indicators monitor device alarm conditions and operating status. ORDERING INFORMATION CDB61310
CS61310 T1 Line Interface Unit l All Required Components for CS61310 Evaluation l LED Status Indications for Alarm Conditions and Operating Status l Support for Hardware and Host Modes
5V+
0V
TCLK TPOS TNEG RCLK RPOS RNEG
TTIP
TRING RTIP
CS61310
RRING MCLK
Hardware Control and Mode Circuit LED Status Indicators Serial Interface Control Circuit XTALOUT XTALIN
+5V
4.7 k
XTL (optional)
P.O. Box 17847, Austin, Texas 78760 (512) 445 7222 FAX: (512) 445 7581 http://www.cirrus.com
Copyright Cirrus Logic, Inc. 2000 (All Rights Reserved)
FEB `00 DS440DB2 1
CDB61310
TABLE OF CONTENTS
1. POWER SUPPLY ..................................................................................................................... 3 2. BOARD CONFIGURATION ...................................................................................................... 3 2.1 Hardware Mode ................................................................................................................. 3 2.1.1 Network Loopback ................................................................................................ 3 2.2 Hardware-Coder Mode ...................................................................................................... 3 2.3 Host Mode ......................................................................................................................... 3 3. TRANSMIT CIRCUIT ................................................................................................................ 3 4. RECEIVE CIRCUIT ................................................................................................................... 4 5. REFERENCE CLOCK .............................................................................................................. 4 5.1 Quartz Crystal .................................................................................................................... 4 5.2 External Reference ............................................................................................................ 4 5.3 LED Indicators ................................................................................................................... 4 6. BUFFERING ............................................................................................................................. 4 7. TRANSFORMER SELECTION ................................................................................................. 4 8. PROTOTYPING AREA ............................................................................................................. 5 9. EVALUATION HINTS ............................................................................................................... 5 10. CDB61310 SOFTWARE ......................................................................................................... 6 10.1 Configure PC ................................................................................................................... 6 10.2 Configure Part .................................................................................................................. 6 10.3 Control Register Configuration ......................................................................................... 6 10.4 Transmitter Ram Configuration ........................................................................................ 6 10.5 Modify Unit Interval .......................................................................................................... 7
LIST OF FIGURES
Figure 1. Register Configuration Window........................................................................................ 7 Figure 2. Transmitter RAM Configuration Window.......................................................................... 8 Figure 3. Modify Unit Interval Window............................................................................................. 9 Figure 4. CDB61310 Evaluation Board Schematic ....................................................................... 10 Figure 5. Board Layout - Top Layer .............................................................................................. 11 Figure 6. Board Layout - Bottom Layer ......................................................................................... 12 Figure 7. Evaluation Board Silkscreen .......................................................................................... 13
LIST OF TABLES
Table 1. LATN Settings ................................................................................................................... 4 Table 2. Transformer and Resistor Default Settings ....................................................................... 4 Table 3. Jumper Selections............................................................................................................. 5
Contacting Cirrus Logic Support
For a complete listing of Direct Sales, Distributor, and Sales Representative contacts, visit the Cirrus Logic web site at: http://www.cirrus.com/corporate/contacts/
Preliminary product information describes products which are in production, but for which full characterization data is not yet available. Advance product information describes products which are in development and subject to development changes. Cirrus Logic, Inc. has made best efforts to ensure that the information contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided "AS IS" without warranty of any kind (express or implied). No responsibility is assumed by Cirrus Logic, Inc. for the use of this information, nor for infringements of patents or other rights of third parties. This document is the property of Cirrus Logic, Inc. and implies no license under patents, copyrights, trademarks, or trade secrets. No part of this publication may be copied, reproduced, stored in a retrieval system, or transmitted, in any form or by any means (electronic, mechanical, photographic, or otherwise) without the prior written consent of Cirrus Logic, Inc. Items from any Cirrus Logic website or disk may be printed for use by the user. However, no part of the printout or electronic files may be copied, reproduced, stored in a retrieval system, or transmitted, in any form or by any means (electronic, mechanical, photographic, or otherwise) without the prior written consent of Cirrus Logic, Inc.Furthermore, no part of this publication may be used as a basis for manufacture or sale of any items without the prior written consent of Cirrus Logic, Inc. The names of products of Cirrus Logic, Inc. or other vendors and suppliers appearing in this document may be trademarks or service marks of their respective owners which may be registered in some jurisdictions. A list of Cirrus Logic, Inc. trademarks and service marks can be found at http://www.cirrus.com.
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1. POWER SUPPLY
As shown on the evaluation board schematic in Figure 1, power is supplied to the board from an external +5 Volt supply connected to the two binding posts labeled V+ and GND. Zener diode Z1 protects the components on the board from reversed supply connections and over-voltage damage. Capacitor C1 provides power supply decoupling and ferrite bead L1 helps isolate the CS61310 and buffer supplies. The 0.1F capacitors decouple their respective ICs. Ferrite bead L7 helps isolates the +5V power into the board. es RLOOP, LLOOP and TAOS on SW1, pulling them high, and then pulling them back to low by opening the RLOOP, LLOOP and TAOS switches in that order. NLOOP can then be turned on by sending the 1:4 pattern to the receive input (RTIP and RRING) for five seconds. If HDR6 is jumped to the NLOOP_LED position, the NLOOP LED will light up. NLOOP can be turned off by sending a 1:2 pattern to RTIP and RRING for five seconds.
2.2
Hardware-Coder Mode
This mode is essentially the same as the Hardware mode with the B8ZS encoder/decoder enabled.
2. BOARD CONFIGURATION
Slide switch S1 selects hardware, host or hardwarecoder mode operation by sliding it into HW, SW or HWCDR positions, respectively.
2.3
Host Mode
2.1
Hardware Mode
In Hardware mode operation, the evaluation board is configured using the DIP switch SW1. In this mode, the switch establishes the digital control inputs for both line interface channels. Closing a DIP switch away from the label sets the CS61310 control pin of the same name to a logic 1. The host processor interface J1 should not be used in the Hardware mode. The CDB61310 switches and functions are listed below:
- TAOS: transmit all ones; - LLOOP: local loopback; - RLOOP: remote loopback; - JASEL: jitter attenuator path selection; - LBO1, LBO2: line build out settings.
In Host mode operation, the evaluation board can be accessed by a PC through the parallel printer port. Connector J1 on the evaluation board is connected to the host PC using a standard DB-25 male-to-female cable (included). Ferrite beads L2 through L6 help reduce noise coming from the PC. The SW1 switch must be open to allow serial port operation. An external microprocessor may also interface to the serial port of the CS61310 through HDR12. In this mode HDR6 should be jumpered so the INT pin comes out at HDR12.
3. TRANSMIT CIRCUIT
The transmit clock and data signals are supplied on BNC inputs labeled TCLK, TPOS, and TNEG. In Hardware and Host mode (with coder mode disabled), data is supplied on the TPOS and TNEG BNC inputs. In Host mode with coder mode enabled, data is supplied on the TDATA BNC input. The transmitter output is transformer coupled to the line through the step-up transformer T2. The signal is available at the Transmit test points, binding posts (J11, J13) or the Transmit bantam jack. Capacitor C12 prevents output stage imbalances from producing a DC current that may saturate the transformer, thus degrading its performance.
All switch inputs are pulled high through resistor R13 when the switch is closed.
2.1.1
Network Loopback
NLOOP is enabled in the hardware mode by shorting HDR11 (HW_NLOOP) and then pressing S2. NLOOP can also be enabled by closing the switch-
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CDB61310
4. RECEIVE CIRCUIT
The receive signal is input at either the Receive test points, binding posts (J4, J10) or the Receive bantam jack. The receive signal is transformer coupled to the CS61310 through the transformer T1. The receive line is terminated by resistors R1-R2 to provide impedance matching and receiver return loss. They are socketed so the values may be changed according to the application. The evaluation board is supplied from the factory with 50 resistors for terminating a 100 twisted-pair T1 line. Capacitor C3 provides an AC ground reference for the differential input. The recovered clock and data signals are available on BNC outputs labeled RCLK, RPOS, and RNEG. In Hardware and Host mode (with coder mode disabled), data is available on the RPOS and RNEG BNC. With coder mode enabled, data is available on the RDATA BNC output in unipolar format and bipolar violations are reported on the RNEG BNC connector. be jumpered in the "MCLK" position to provide connectivity to the MCLK pin of the CS61310.
5.3
LED Indicators
The four-LED pack D1 indicates signal states on LATN1, LATN2, LOS and NLOOP. The LOS LED indicator illuminates when the line interface receiver has detected a loss of signal. The NLOOP LED indicates if Network Loopback is in operation. The LATN1/LATN2 LED's indicate the attenuation level of the received signal below the nominal signal level. See Table 1 for details.
LATN1 ON OFF ON OFF LATN2 ON OFF OFF ON Attenuation Level (dB) 0 7.5 15 22.5
Table 1. LATN Settings
6. BUFFERING
Buffer U2 provides additional drive capability for the SW1 and Host mode connections. The buffer outputs are filtered with an (optional) RC network (not initially populated) to reduce the transients caused by buffer switching.
5. REFERENCE CLOCK
The CDB61310 requires a T1 reference clock for operation. This clock can be supplied by either a quartz crystal or an external reference. The evaluation board is supplied from the factory with a quartz crystal for T1 operations. In the case that both the external reference and the quartz crystal are applied, the external reference takes precedence.
7. TRANSFORMER SELECTION
The evaluation board is supplied from the factory with PE-64936 (1:1) and PE-65351 (1:2) transformers by Pulse Engineering. The socket T1 on the board is for the receive transformer and T2 is for transmit. Please see Table 2 for details on transformers selection.
TX RX Transformer Transformer R1-R2 R3-R4 1:2 1:1 50 9.1
5.1
Quartz Crystal
A quartz crystal may be inserted at socket Y1. The quartz crystals operate at 4X the frequency of operation, or 6.176 MHz. HDR9 allows the XTAL_IN pin to be pulled high or low to disable or enable the jitter attenuator.
Mode T1 (100 )
5.2
External Reference
Table 2. Transformer and Resistor Default Settings
An external reference of 1.544 MHz may be provided at the REFCLK BNC input. Header HDR7 must
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CDB61310
8. PROTOTYPING AREA
A prototyping area with power supply and ground connections is provided on the evaluation board. This area can be used to develop and test a variety of additional circuits such as framer devices, system synchronizer PLLs, or specialized interface logic. 3) Closing a DIP switch on SW1 sets the CS61310 control pin of the same name to logic 1. 4) When performing a manual loopback of the recovered signal to the transmit signal at the BNC connectors, the recovered data must be valid on the falling edge of RCLK to properly latch the data in the transmit direction. 5) A jumper can be placed on header HDR4 to provide a ground reference on TRING. Properly terminate TTIP/TRING when evaluating the transmit output pulse shape. For more information concerning pulse shape evaluation, refer to the Crystal application note AN07 entitled "Measurement and Evaluation of Pulse Shapes in T1/E1 Transmission Systems."
9. EVALUATION HINTS
1) The orientation of pin 1 for the CS61310 is marked by a small circle on the top-left side of the socket U1. 2) Component locations R1-R4, Y1, T1 and T2 must have the correct values installed according to the application. All the necessary components are included with the evaluation board.
Jumper HDR4 HDR5 HDR6 HDR7 HDR8 HDR9 HDR10 HDR11 HDR12
Position IN IN INT GND MCLK IN XTAL-HI XTAL-GND IN OUT IN X
Selection Grounds TRING on the line side of the transmit transformer Grounds the line side of RRING through C2 Host Mode operation, connects INT pin to the serial interface Grounds the MCLK pin Connects the MCLK pin to the BNC Pulls the TNEG pin high, for selecting the coder mode (TCLK has to be present to select Coder Mode) Pulls the pin XTALIN high Pulls the pin XTALIN to ground Must be shorted for Host Mode (TAOS/CLKE pin) or Hardware Mode (for DIP switch). Allows S2 to pull RLOOP and LLOOP high for RESET in Hardware Mode Allows S2 to pull RLOOP, LLOOP, and TAOS high for enabling NLOOP in hardware mode Not a jumper: provides access to the serial port signals plus signal grounds for cable. Table 3. Jumper Selections
NLOOP_LED Hardware Mode operation, connects NLOOP pin to the LED
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CDB61310
10. CDB61310 SOFTWARE
The CDB61310 can be configured in the host/software mode using the application CDB61310.EXE supplied with the board. This application allows the user to access all of the user programmable registers in the device. The program supplied with the board runs under Windows 95 and 98. A special version for Windows NT is available from the factory. Contact your nearest Cirrus Logic representative for details. CDB61310 evaluation board. Before using this method, the user is advised to disconnect all other devices from the LPT ports.
10.2
Configure Part
10.1
Configure PC
The Configure_Part pull down menu has two options. The first is Control Register Configuration, which gives access to the control and status registers. The second is Transmitter RAM Configuration, which configures the Arbitrary Waveform Generator (AWG). See the CS61310 data sheet for information on programming these registers.
This function allows the user to set the address of the PC parallel port. The selection depends on the configuration of the user's PC. The Plug and Play (PnP) function of the operating system determines this address every time the PC is powered up, but it normally won't change the printer port address unless the configuration of the hardware has changed. There are two ways to determine the address of the parallel port: the safe method and the fast method. The safe method is to double click on the My Computer icon on the desktop, double click on Control panel, then Double click on System. Select the Device Manager tab, then with "View devices by type" selected in the window that pops up, double click on Ports (COM & LPT). Click on the Printer Port icon that corresponds to the port that is connected to the CDB61310 evaluation board, then select Properties. On the Properties window, select the Resources tab, then read the I/O address in the Input/Output Range field. This is the address range to select for the CDB61310. The fast method is to try the ports one by one, going to the Configure Part window every time to see which one allows the user to read from the device. when the wrong address is selected, the bit fields in this window will read either all zeroes or all ones. Going to the Configure Part window automatically issues a read command to the device, which will cause unpredictable results if the selected LPT port is connected to some device other than a
6
10.3
Control Register Configuration
Selecting Control Register Configuration pulls up the register configuration window and automatically issues a read command to the CDB61310; the user must make sure that the software is configured to use the proper LPT port before this option is selected (see Configure PC above). The register configuration window is shown in Figure 1 on page 7. The bits in the Control Registers (CNTL REG 1, CNTL REG 2, CNTL REG 3) are written by checking the box opposite to the individual bits in the "Write" columns, then clicking on the "Write Registers" button. This writes the displayed data to all three control registers, then automatically reads the control and status registers and displays the results in the "Read" columns. Since Control Register 1 is effectively a control register when it is written and a status register when it is read, the read status is decoded and displayed in the Read Status window. The registers can also be read by clicking on the "Read Registers" button. All five registers are read when this command is selected. The LATN REG register shows the current setting of the gain equalizer.
10.4
Transmitter Ram Configuration
When this command is selected, the software pops up a window which displays the contents of the
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CDB61310
AWG RAM (see Figure 2 on page 8). Notice the six buttons along the bottom of this window. Modify Unit Interval brings up the Transmitter RAM UI Config window, which allows the user to edit the contents of the AWG registers. It is described in the following section. Read from File reads previously generated data from a file. Load to File writes the currently displayed data into a file for later recovery using the Read from File command. Read from RAM reads the current data from the AWG RAM and displays it in the current window. Write to RAM writes the displayed data to the AWG RAM. This must be done before exiting to write the data to the device. Exit returns control to the main CDB61310 menu. It does not automatically write the data to the CS61310.
10.5
Modify Unit Interval
The user modifies the data in the AWG RAM using the Transmitter RAM UI Config window (see Figure 3 on page 9). At the top of this window are three radio buttons used for selecting one of the three unit intervals. At the lower right is another set of radio buttons, one for each of the prestored waveforms in ROM (config 2 through config f). After having selected the desired UI and line configuration, clicking on the Read button will display the
Figure 1. Register Configuration Window DS440DB2 7
CDB61310
contents of the given waveform in the Time Slot fields. These values are displayed in hexadecimal format. The user can modify these values by clicking on the selection arrow and scrolling up and down through the possible values. After making the necessary modifications, the user clicks the "Save to UI" button to save the data for that UI to the PC's memory. When all three UI's have been saved, the new values are written to the AWG RAM on the device by going back to the Transmitter RAM Configuration window and clicking on the Write to RAM button. These settings are reset to the initial state when the window is closed. The Save Screen and Restore Scrn buttons must be used if the user wishes to exit this window and come back to the same setup.
Figure 2. Transmitter RAM Configuration Window
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CDB61310
Figure 3. Modify Unit Interval Window
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FERRITE_BEAD
2 4 6 8 10
HDR12 HDR5X2 DB25M_RA P1 1 14 2 15 3 16 4 17 5 18 6 19 7 20 8 21 9 22 10 23 11 24 12 25 13
GND
1 3 5 7 9
L7
TNEG
TPOS
TCLK
MCLK
SDO
NLOOP_LED
1
INT
47 COG 100PF
SW HW HWCDR GND
RNEG 1 3 4
3
2
FERRITE_BEAD
SDI SCLK/LLOOP
4
TCLK
MCLK
TNEG/UBS
TAOS/CLKE
TPOS/TDATA
LLOOP/SCLK
RLOOP/CS
C8
GND
GND
GND
COG 100PF
INT SDO
FERRITE_BEAD L5 L6
9
1
XTAL_GND
XTAL_HI
COG 100PF
R9
47 GND COG 100PF
3
R10
47
HDR9 10
XTALIN XTALOUT JASEL
SKT_PLCC28_ECM
RV+ RRING RTIP
21 20 19
+5V
C9
2
4
TRING
C16
TTIP
TGND
GND +5V
R6 4.7K
C10
6.1760MHZ
GND
LATN
LOS
TV+
N/C
COG 100PF
100
C11
R13
OPEN
U3
RCLK LATN
1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13
SW_DIP_6 HDR1X2 HDR10 1 2 1N4148 D6 RN1 47K D7
C7
HW_RST/NLOOP
HWMODE
R12 100 S2 SW_B3W_1100
+5V GND
2 3 4 5 6 7 8 9
.1UF U5
GND
1 19
1N4148
R16 VCC Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 GND
20
47 47 COG 100PF 47 COG 100PF C22 47 COG 100PF C18 47 COG 100PF C20 47 COG 100PF C21 C19 COG 100PF
C13 .1UF
GND
1N4148 D8
/G1 /G2 A1 A2 A3 A4 A5 A6 A7 A8
R19
18 17 16 15 14 13 12 11 10
R15 R17 R18 R14
GND
PALCE20RA10H
GND
GND
U4
11 10
VCC
1
14
U4
2
GND
MC74F14N U4
13 12
GND
SN74HCT541N
GND
MC74F14N GND
7
C17
GND GND
MC74F14N
GND
LED_555_5003
+5V
GND LATN1
U4
3 4
5 6 7
4
LATN2
3
MC74F14N U4
5 6
LOS
2
NLOOP
8 1
MCLK
TCLK
TPOS
TNEG
RNEG
RPOS
RCLK
MC74F14N U4
BNC
BNC
BNC
BNC
BNC
J7
J5
BNC
BNC
D1
J9
J8
J12
J2
J6
GND
10
J18 J19
+5V
GND
Z1 HDR7
P6KE6V8P
GND
+5V
GND
1 3 2 4
L1 FERRITE_BEAD
C1
HDR8 1 2
47UF
+5V GND RRING TP1
6 HDR5 HDR1X2 6 7 8 9 10 1
R5 1K
+5V
U2
SCLK
TNEG_HI
RECEIVE
L2
SDI
FERRITE_BEAD L3 FERRITE_BEAD L4
CS
1 19 2 3 4 5 6 7 8 9
/G1 /G2 A1 A2 A3 A4 A5 A6 A7 A8
VCC Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 GND
20
INT CS
18 17 16 15 14 13 12 11 10
C15 .1UF R7
+5V
R1 49.9 C3
HDR6
5
J3
2
3
S1
2
4
3
2
1
28
27
26
.47UF R2 GND 49.9
1 PE_64936 T1
2
TP2
RTIP
CON_RTT87 C2 47PF COG
RTIP
J4
SW_SP3T
5 6
GND
MODE
L802/ SDO
25 24 23 22
SN74HCT541N
R8
47
C4 .1UF
V+
JP8
J10
RNEG/BPV RPOS/RDATA
L801/SDI NLOOP/INT
GND RRING
RPOS RCLK
7 8
U1
RCLK
CS61310
RGND
RRING RTIP
Y1
FERRITE_BEAD
11
R3
V+ +5V
JP9
9.09
2 1
TRING TP3
1 2 3 4 5
TRANSMIT
J3
GND
GND
12
13
14
15
16
17
18 TTIP LATN TRING
GND
C5 .1UF
R11
47
+5V
C6 47UF C12 .47UF
3
R4
9.09
6 T2 PE_65351 5
TTIP TP4
CON_RTT87
TTIP
J13 1 2
GND
HDR4 HDR1X2
J11
SW1
6 5 4 3 2 1
TAOS LLOOP RLOOP LBO2 LBO1 JASEL
GND
GND
C14
.1UF
TRING
2 1
HDR11
HW NLOOP
CDB61310
9
8
MC74F14N
GND
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Figure 4. CDB61310 Evaluation Board Schematic
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CDB61310
Figure 5. Board Layout - Top Layer
11
12
CDB61310
DS440DB2
Figure 6. Board Layout - Bottom Layer
DS440DB2
CDB61310
Figure 7. Evaluation Board Silkscreen
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